The invention relates to use of doped polycrystalline silicon (polysilicon) vias to provide electrical connection between vertically separate polysilicon layers, specifically polysilicon channel layers in transistors, gate electrodes, and other device elements.
When an electrical connection needs to be made between vertically separate layers in a semiconductor device, a vertical interconnect or via is typically formed of a conductive material to connect them.
The typical method of formation is to form the lower layer to which connection is needed, then cover it with an insulating layer. Next a hole or void is excavated in the insulating layer, and the void is filled with a conductive material, forming the via. The upper layer to which conduction is needed is then formed above and in contact with the via. Alternately, the via and the upper conductive layer can be formed of the same material, in a single deposition step.
Among the most common materials used for vias is tungsten. Tungsten vias or plugs are not compatible with all devices and materials, however.
There is a need, therefore, for other methods and materials to be used for forming vias in semiconductor structures.